1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and, more particularly, to an improved method for forming a deep trench structure having an improved spacer isolation.
2. Background of Invention
Capacitors may be found in a variety of semiconductor circuits. In general, capacitors include two electrodes separated by some barrier (e.g. node dielectric) used to isolate the two electrodes from one another. As the physical size of these devices continue to shrink, the need for perfect isolation between the capacitor electrodes becomes increasingly more important. A deep trench capacitor may be formed in a bulk SOI substrate. The bulk SOI substrate may have an SOI layer stacked on top of a buried oxide layer and the buried oxide layer stacked on top of a base substrate. The base substrate generally being n-doped silicon and the SOI layer generally being p-doped silicon. A pad layer may also be located atop the bulk SOI substrate. Deep trench capacitors may be formed through the pad layer and into all layers of the bulk SOI substrate. Therefore the base substrate may act as one of the capacitor's two electrodes while a conductive layer may act as the other electrode. Isolation between the base substrate and the conductive layer may be critical.
A short circuit may result should any portion of the node dielectric be removed from below the BOX layer because a barrier would no longer insulate the base substrate from the conductive layer. Therefore, the recess depth of the polysilicon may directly affect whether the deep trench capacitor functions properly or fails due to a short circuit. Current processing techniques are imperfect. Recess depth control may be one challenge in fabricating deep trench capacitors in SOI substrates. These challenges may be further magnified as the semiconductor structures continue to decrease in size.